Physical design method of MPSoC

Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel diagonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network containing hand-adjusted buffers and variable routing rules is cons...

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Bibliographic Details
Published inJournal of Zhejiang University. A. Science Vol. 8; no. 4; pp. 631 - 637
Main Authors Liu, Peng, Xia, Bing-jie, Teng, Zhao-wei
Format Journal Article
LanguageEnglish
Published Department of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China 01.04.2007
Subjects
平面布置图
快速原型制作
片上多处理器系统
物理设计方法
Floorplan
Clock tree synthesis (CTS)
Multiprocessor system-onchip (MPSoC)
Power plan
Fast prototyping
Physical design
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Summary:Floorplan, clock network and power plan are crucial steps in deep sub-micron system-on-chip design. A novel diagonal floorplan is integrated to enhance the data sharing between different cores in system-on-chip. Custom clock network containing hand-adjusted buffers and variable routing rules is constructed to realize balanced synchronization. Effective power plan considering both IR drop and electromigration achieves high utilization and maintains power integrity in our MediaSoC. Using such methods, deep sub-micron design challenges are managed under a fast prototyping methodology, which greatly shortens the design cycle.
Bibliography:TN47
Physical design, Fast prototyping, Floorplan, Clock tree synthesis （CTS）, Power plan, Multiprocessor system-onchip （MPSoC）
33-1236/O4
ISSN:1673-565X
1862-1775
DOI:10.1631/jzus.2007.A0631