A BiCMOS PLL-based data separator circuit with high stability and accuracy

• Published in: IEEE journal of solid-state circuits Vol. 26; no. 2; pp. 116 - 121
• Main Authors: Miyazawa, S., Horita, R., Hase, K., Kato, K., Kojima, S.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.02.1991; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; BiCMOS integrated circuits; Circuit stability; Decoding; Detectors; Disk drives; Electronics; Exact sciences and technology; Frequency synchronization; Magnetic and optical mass memories; Particle separators; Phase detection; Phase locked loops; Storage and reproduction of information; Winches; Phase detector; Circuit design; Electric scheme; Integrated circuit; BiCMOD technology; Data processing; Magnetic disk; Hardware; Phase locked loop
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.68125

A data separator that can work in Winchester disk drives at a read/write speed of up to 30 Mb/s is described. To realize high stability and accuracy in reproducing data in high-speed transfers, a digital synchronization field detector and an analog dual-mode phase-locked loop (PLL) that has a phase detector which has constant gain in the data field, independent of pattern, are used. The dual-mode analog PLL has a wide decode margin, locks up quickly, and operates stably without being affected by the frequency deviation of data. The digital sync field detector is adjustment-free and detects sync fields very accurately. The IC incorporates a RLL 2-7 code encoder/decoder and a write compensator. Use of the 2- mu m BiCMOS process keeps the total power consumption as low as 400 mW even at the high transfer rate of 30 Mb/s.< >