An experimental 1.5-V 64-Mb DRAM

• Published in: IEEE journal of solid-state circuits Vol. 26; no. 4; pp. 465 - 472
• Main Authors: Nakagome, Y., Tanaka, H., Takeuchi, K., Kume, E., Watanabe, Y., Kaga, T., Kawamoto, Y., Murai, F., Izawa, R., Hisamoto, D., Kisu, T., Nishida, T., Takeda, E., Itoh, K.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.04.1991; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Charge pumps; Data communication; Delay; DRAM chips; Driver circuits; Electronics; Exact sciences and technology; Interference; Low voltage; Power supplies; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal to noise ratio; Characterization; Low voltage; Random access memory(RAM); Power supply; Response time; Dynamical storage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.75040

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 mu m/sup 2/ crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 mu m electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs.< >