Design and performance analysis of Dual-Gate All around Core-Shell Nanotube TFET
In this research work, we have put forward Silicon based Nanotube structure with Dual Gate All around configuration. The proposed device has been compared with Conventional Nanowire structure and the comparison is concocted on account of analog parameters of both the devices. The structural paramete...
Saved in:
| Published in | Superlattices and microstructures Vol. 125; pp. 356 - 364 |
|---|---|
| Main Authors | , , , |
| Format | Journal Article |
| Language | English |
| Published |
Elsevier Ltd
01.01.2019
|
| Subjects | |
| Online Access | Get full text |
Cover
Loading…
| Abstract | In this research work, we have put forward Silicon based Nanotube structure with Dual Gate All around configuration. The proposed device has been compared with Conventional Nanowire structure and the comparison is concocted on account of analog parameters of both the devices. The structural parameters of both the devices are kept identical like work function, doping concentrations of Source, Channel and Drain regions. By using an inner core gate and an outer shell gate, the proposed device exhibited superior Analog characteristics over its Nanowire counterpart in terms of drive current (ION), Electrical criteria, capacitance, unity gain, and transconductance.
•Dual Gate All around configuration over Tunnel FET is proposed and investigated.•Various analog/RF and process parameters are extracted and discussed.•Compared with Conventional Nanowire structure. |
|---|---|
| AbstractList | In this research work, we have put forward Silicon based Nanotube structure with Dual Gate All around configuration. The proposed device has been compared with Conventional Nanowire structure and the comparison is concocted on account of analog parameters of both the devices. The structural parameters of both the devices are kept identical like work function, doping concentrations of Source, Channel and Drain regions. By using an inner core gate and an outer shell gate, the proposed device exhibited superior Analog characteristics over its Nanowire counterpart in terms of drive current (ION), Electrical criteria, capacitance, unity gain, and transconductance.
•Dual Gate All around configuration over Tunnel FET is proposed and investigated.•Various analog/RF and process parameters are extracted and discussed.•Compared with Conventional Nanowire structure. |
| Author | Amin, S. Intekhab Mushtaq, Umar Kumar, Naveen Anand, Sunny |
| Author_xml | – sequence: 1 givenname: Naveen surname: Kumar fullname: Kumar, Naveen organization: Dr. B. R. Ambedkar National Institute of Technology Jalandhar, India – sequence: 2 givenname: Umar surname: Mushtaq fullname: Mushtaq, Umar organization: Amity University, Sector-125, Noida, Uttar Pradesh, India – sequence: 3 givenname: S. Intekhab surname: Amin fullname: Amin, S. Intekhab organization: Jamia Milia Islamia, Jamia Nagar, New Delhi, India – sequence: 4 givenname: Sunny surname: Anand fullname: Anand, Sunny email: sunnyanand.42@gmail.com organization: Amity University, Sector-125, Noida, Uttar Pradesh, India |
| BookMark | eNp9kMFKw0AQhhepYFt9AU95gcTZJN1kwUtptQpFBet5mWxmdUuaLbup0Ld3Sz158DTMz_8NzDdho971xNgth4wDF3fbLOx3NsuB1xnIDHh-wcYcpEgLUVUjNoaqlKmAQlyxSQhbAJAlr8bsbUnBfvYJ9m2yJ2-c32GvKe7YHYMNiTPJ8oBdusKBknnXJejdIZYXzlP6_kUxecHeDYeGks3jw-aaXRrsAt38zin7iOniKV2_rp4X83WqC4AhbaVsGtQaTTNrjGy4ROC6LFqRx7CpUMzKGgTNsOQo2lpTzrGuORDUxpAspiw_39XeheDJqL23O_RHxUGdnKitOjlRJycKpIpOIlT_gbQdcLCuHzza7n_0_oxSfOrbkldBW4qqWutJD6p19j_8B6oFgDE |
| CitedBy_id | crossref_primary_10_1016_j_micrna_2024_207995 crossref_primary_10_1007_s12633_022_01720_9 crossref_primary_10_1007_s42341_024_00523_6 crossref_primary_10_1007_s12633_019_00350_y crossref_primary_10_1038_s41699_022_00352_2 crossref_primary_10_1007_s00339_019_2700_z crossref_primary_10_1007_s12633_021_01404_w crossref_primary_10_1007_s12633_022_01866_6 crossref_primary_10_1007_s00034_025_03047_3 crossref_primary_10_1016_j_spmi_2020_106522 crossref_primary_10_1109_TED_2019_2924809 crossref_primary_10_1007_s10825_020_01574_7 crossref_primary_10_1016_j_mejo_2023_105990 crossref_primary_10_1109_JSEN_2019_2944885 crossref_primary_10_1088_2053_1591_ab30b0 crossref_primary_10_1038_s41598_023_38239_x crossref_primary_10_1080_03772063_2024_2368636 crossref_primary_10_1007_s12633_020_00705_w crossref_primary_10_1007_s12648_020_01776_6 crossref_primary_10_1007_s11664_020_08572_2 crossref_primary_10_1007_s00542_019_04666_y crossref_primary_10_1016_j_rinp_2022_105312 crossref_primary_10_3390_mi14071335 crossref_primary_10_1016_j_micrna_2024_207933 crossref_primary_10_1007_s12633_020_00654_4 crossref_primary_10_1007_s12633_020_00882_8 crossref_primary_10_1109_TED_2020_2965244 crossref_primary_10_1007_s00339_021_05100_9 crossref_primary_10_1007_s12633_020_00777_8 crossref_primary_10_1149_2162_8777_aca2da crossref_primary_10_3390_mi10110749 crossref_primary_10_1007_s12633_021_01102_7 crossref_primary_10_1007_s12633_023_02575_4 crossref_primary_10_1007_s12633_022_01674_y crossref_primary_10_1049_cds2_12064 crossref_primary_10_1007_s00366_021_01530_4 crossref_primary_10_1007_s11664_021_09072_7 crossref_primary_10_1149_2162_8777_ad5c9d crossref_primary_10_1016_j_mejo_2024_106192 crossref_primary_10_1088_1361_6641_ac86e9 crossref_primary_10_1109_TNB_2022_3216505 crossref_primary_10_1007_s12633_021_00956_1 crossref_primary_10_1016_j_matpr_2022_09_449 crossref_primary_10_1016_j_micrna_2024_207989 crossref_primary_10_1007_s12633_020_00376_7 crossref_primary_10_1007_s11220_023_00455_0 crossref_primary_10_1007_s10825_021_01696_6 crossref_primary_10_1007_s12633_020_00584_1 crossref_primary_10_1007_s12633_022_01839_9 crossref_primary_10_1007_s00339_021_04388_x crossref_primary_10_1109_TNANO_2022_3208208 crossref_primary_10_1007_s00339_020_03736_7 crossref_primary_10_1109_TNB_2022_3172702 |
| Cites_doi | 10.1038/nnano.2010.15 10.1109/TED.2005.846318 10.1109/TED.2010.2089525 10.1109/TED.2007.899389 10.1109/LED.2009.2021079 10.1038/nature10679 10.1016/j.sse.2005.10.045 10.1109/LED.2011.2165331 10.1109/TED.2013.2243151 10.1109/LED.2007.901273 10.1109/LED.2008.2007599 10.1063/1.2981088 10.1109/TVLSI.2013.2293135 10.1007/s10825-016-0859-5 |
| ContentType | Journal Article |
| Copyright | 2018 Elsevier Ltd |
| Copyright_xml | – notice: 2018 Elsevier Ltd |
| DBID | AAYXX CITATION |
| DOI | 10.1016/j.spmi.2018.09.012 |
| DatabaseName | CrossRef |
| DatabaseTitle | CrossRef |
| DatabaseTitleList | |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Chemistry Physics |
| EISSN | 1096-3677 |
| EndPage | 364 |
| ExternalDocumentID | 10_1016_j_spmi_2018_09_012 S0749603618315726 |
| GroupedDBID | --K --M -~X .~1 0R~ 123 1B1 1RT 1~. 1~5 29Q 4.4 457 4G. 5VS 7-5 71M 8P~ 9JN AABXZ AACTN AAEDT AAEDW AAEPC AAIAV AAIKJ AAKOC AALRI AAOAW AAQFI AAQXK AAXUO ABFNM ABJNI ABMAC ABNEU ABXDB ABXRA ABYKQ ACDAQ ACFVG ACGFS ACNNM ACRLP ADBBV ADEZE ADFGL ADMUD AEBSH AEKER AENEX AEZYN AFKWA AFRZQ AFTJW AGHFR AGUBO AGYEJ AHHHB AIEXJ AIKHN AITUG AIVDX AJBFU AJOXV ALMA_UNASSIGNED_HOLDINGS AMFUW AMRAJ ASPBG AVWKF AXJTR AZFZN BBWZM BKOJK BLXMC CAG COF CS3 DM4 DU5 EBS EFBJH EFLBG EJD EO8 EO9 EP2 EP3 FDB FEDTE FGOYB FIRID FNPLU FYGXN G-2 G-Q GBLVA HMV HVGLF HZ~ IHE J1W KOM LG5 M24 M37 MAGPM MO0 N9A NDZJH O-L O9- OAUVE OGIMB OZT P-8 P-9 P2P PC. Q38 R2- RIG RNS ROL RPZ SDF SDG SDP SES SEW SMS SPC SPCBC SPD SPG SSM SSQ SSZ T5K UHS WUQ XPP ZMT ZU3 ~G- AATTM AAXKI AAYWO AAYXX ABWVN ACRPL ACVFH ADCNI ADNMO AEIPS AEUPX AFPUW AFXIZ AGQPQ AGRNS AIGII AIIUN AKBMS AKRWK AKYEP ANKPU BNPGV CITATION SSH |
| ID | FETCH-LOGICAL-c300t-d99bbaccafb5bf9b19a01c43d62ccab7a654806e5a41a6d8ce21a8810e08ffe93 |
| IEDL.DBID | .~1 |
| ISSN | 0749-6036 |
| IngestDate | Thu Apr 24 23:05:08 EDT 2025 Tue Jul 01 01:35:11 EDT 2025 Fri Feb 23 02:43:53 EST 2024 |
| IsPeerReviewed | false |
| IsScholarly | false |
| Keywords | Nanowire Dual-Gate All around Core and shell gates TFET Nanotube |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c300t-d99bbaccafb5bf9b19a01c43d62ccab7a654806e5a41a6d8ce21a8810e08ffe93 |
| PageCount | 9 |
| ParticipantIDs | crossref_primary_10_1016_j_spmi_2018_09_012 crossref_citationtrail_10_1016_j_spmi_2018_09_012 elsevier_sciencedirect_doi_10_1016_j_spmi_2018_09_012 |
| ProviderPackageCode | CITATION AAYXX |
| PublicationCentury | 2000 |
| PublicationDate | January 2019 2019-01-00 |
| PublicationDateYYYYMMDD | 2019-01-01 |
| PublicationDate_xml | – month: 01 year: 2019 text: January 2019 |
| PublicationDecade | 2010 |
| PublicationTitle | Superlattices and microstructures |
| PublicationYear | 2019 |
| Publisher | Elsevier Ltd |
| Publisher_xml | – name: Elsevier Ltd |
| References | Sze, Ng (bib8) 2007; vol. 315 Anand, Sarin (bib9) 2016; 15 Choi, Park, Lee, Liu (bib7) Aug 2007; 28 Boucart, MihaiIonescu (bib3) July 2007; 54 Sunny Anand, S. Intekhab Amin, R. K. Sarin: “Analog performance investigation of dual electrode based doping-less tunnel FET” J. Comput. Electron. DOI 10.1007/s10825-015-0771-4. Gandhi, Chen, Singh, Banerjee, Lee (bib15) 2011; 32 Esseni, Guglielmini, Kapidani, Rollo, Alioto (bib6) December 2014; 22 Bhuwalka, Schulze, Eisele (bib2) May 2005; 52 Chen, Yu, Singh, Shen, Sayanthan, Lo, Kwong (bib17) JULY 2009; 30 Chen (bib14) 2009; 30 Fahad, Hussain (bib18) March 2013; 60 Ionescu, Riel (bib16) 2011; 479 Nirschl, Henzler, Fischer, Fulde, Bargagli-Stoffi, Sterkel, Sedlmeir, Weber, Heinrich, Schaper, Einfeld, Neubert, Feldmann, Stahrenberg, Ruderer, Georgakos, Huber, Kakoschke, Hansch, Schmitt-Landsiedel (bib4) 2006; 50 Verhulst (bib13) 2008; 29 Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 2005. Verhulst, Vandenberghe, Maex, Groeseneken (bib12) 2008; 104 Colinge, Lee, Afzalian, Akhavan, Yan, Ferain, Razavi, O'Neill, Blake, White, Kelleher, McCarthy, Murphy (bib1) 2010; 5 Jhaveri, Nagavarapu, Woo (bib11) 2011; 58 Chen (10.1016/j.spmi.2018.09.012_bib14) 2009; 30 Gandhi (10.1016/j.spmi.2018.09.012_bib15) 2011; 32 Jhaveri (10.1016/j.spmi.2018.09.012_bib11) 2011; 58 Ionescu (10.1016/j.spmi.2018.09.012_bib16) 2011; 479 Nirschl (10.1016/j.spmi.2018.09.012_bib4) 2006; 50 Bhuwalka (10.1016/j.spmi.2018.09.012_bib2) 2005; 52 Verhulst (10.1016/j.spmi.2018.09.012_bib13) 2008; 29 Esseni (10.1016/j.spmi.2018.09.012_bib6) 2014; 22 Choi (10.1016/j.spmi.2018.09.012_bib7) 2007; 28 Verhulst (10.1016/j.spmi.2018.09.012_bib12) 2008; 104 Fahad (10.1016/j.spmi.2018.09.012_bib18) 2013; 60 Anand (10.1016/j.spmi.2018.09.012_bib9) 2016; 15 Boucart (10.1016/j.spmi.2018.09.012_bib3) 2007; 54 Chen (10.1016/j.spmi.2018.09.012_bib17) 2009; 30 Colinge (10.1016/j.spmi.2018.09.012_bib1) 2010; 5 Sze (10.1016/j.spmi.2018.09.012_bib8) 2007; vol. 315 10.1016/j.spmi.2018.09.012_bib10 10.1016/j.spmi.2018.09.012_bib5 |
| References_xml | – volume: 54 year: July 2007 ident: bib3 article-title: Member, IEEE, “double gate tunnel FET with high-K gate dielectric” publication-title: IEEE Trans. Electron. Dev. – volume: vol. 315 year: 2007 ident: bib8 publication-title: Physics of Semiconductor Devices – volume: 50 start-page: 44 year: 2006 end-page: 51 ident: bib4 article-title: Scaling properties of the tunneling field effect transistor (TFET): device and circuit publication-title: Solid State Electron. – volume: 32 start-page: 1504 year: 2011 end-page: 1506 ident: bib15 article-title: CMOS-compatible vertical-silicon-nanowire gate-all-around p-type tunneling FETs with ≤ 50-mV/decade subthreshold swing publication-title: IEEE Electron. Device Lett. – volume: 58 start-page: 80 year: 2011 end-page: 86 ident: bib11 article-title: Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor publication-title: IEEE Trans. Electron. Dev. – volume: 22 year: December 2014 ident: bib6 article-title: “Tunnel FETs for ultralow voltage digital VLSI circuits: Part I—device–Circuit interaction and evaluation at device level” publication-title: IEEE Trans. Very Large Scale Integr. Syst. – volume: 30 year: JULY 2009 ident: bib17 article-title: Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires publication-title: IEEE Electron. Device Lett. – volume: 60 year: March 2013 ident: bib18 article-title: High-performance silicon nanotube tunneling FET for ultralow-power logic applications publication-title: IEEE Trans. Electron. Dev. – volume: 30 start-page: 754 year: 2009 end-page: 756 ident: bib14 article-title: Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires publication-title: IEEE Electron. Device Lett. – volume: 15 start-page: 850 year: 2016 end-page: 856 ident: bib9 article-title: Analog and RF performance of doping-less tunnel FETs with Si publication-title: J. Comput. Electron. – volume: 479 start-page: 329 year: 2011 end-page: 337 ident: bib16 article-title: Tunnel field-effect transistors as energy-efficient electronic switches publication-title: Nature – reference: Sunny Anand, S. Intekhab Amin, R. K. Sarin: “Analog performance investigation of dual electrode based doping-less tunnel FET” J. Comput. Electron. DOI 10.1007/s10825-015-0771-4. – volume: 28 start-page: 743 year: Aug 2007 end-page: 745 ident: bib7 article-title: Tunneling field-effect transistors with subthreshold swing less than 60mV/dec publication-title: IEEE Electron. Device Lett. – volume: 104 year: 2008 ident: bib12 article-title: Boosting the on-current of a n-channel nanowire tunnel field-effect publication-title: J. Appl. Phys. – reference: Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 2005. – volume: 52 start-page: 909 year: May 2005 end-page: 917 ident: bib2 article-title: Scaling the vertical tunnel FET with tunnel bandgap modulation and gate work function engineering publication-title: IEEE Trans. Electron. Dev. – volume: 29 start-page: 1398 year: 2008 end-page: 1401 ident: bib13 article-title: Complementary silicon-based heterostructure tunnel-FETs with high tunnel rates publication-title: IEEE Electron. Device Lett. – volume: 5 start-page: 225 year: 2010 end-page: 229 ident: bib1 article-title: Nanowire transistors without junctions publication-title: Nat. Nanotechnol. – volume: 5 start-page: 225 issue: 3 year: 2010 ident: 10.1016/j.spmi.2018.09.012_bib1 article-title: Nanowire transistors without junctions publication-title: Nat. Nanotechnol. doi: 10.1038/nnano.2010.15 – volume: 52 start-page: 909 issue: 5 year: 2005 ident: 10.1016/j.spmi.2018.09.012_bib2 article-title: Scaling the vertical tunnel FET with tunnel bandgap modulation and gate work function engineering publication-title: IEEE Trans. Electron. Dev. doi: 10.1109/TED.2005.846318 – volume: 58 start-page: 80 issue: 1 year: 2011 ident: 10.1016/j.spmi.2018.09.012_bib11 article-title: Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor publication-title: IEEE Trans. Electron. Dev. doi: 10.1109/TED.2010.2089525 – volume: 54 issue: 7 year: 2007 ident: 10.1016/j.spmi.2018.09.012_bib3 article-title: Member, IEEE, “double gate tunnel FET with high-K gate dielectric” publication-title: IEEE Trans. Electron. Dev. doi: 10.1109/TED.2007.899389 – volume: vol. 315 year: 2007 ident: 10.1016/j.spmi.2018.09.012_bib8 – ident: 10.1016/j.spmi.2018.09.012_bib10 – volume: 30 start-page: 754 year: 2009 ident: 10.1016/j.spmi.2018.09.012_bib14 article-title: Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires publication-title: IEEE Electron. Device Lett. doi: 10.1109/LED.2009.2021079 – volume: 479 start-page: 329 year: 2011 ident: 10.1016/j.spmi.2018.09.012_bib16 article-title: Tunnel field-effect transistors as energy-efficient electronic switches publication-title: Nature doi: 10.1038/nature10679 – volume: 50 start-page: 44 issue: 1 year: 2006 ident: 10.1016/j.spmi.2018.09.012_bib4 article-title: Scaling properties of the tunneling field effect transistor (TFET): device and circuit publication-title: Solid State Electron. doi: 10.1016/j.sse.2005.10.045 – volume: 32 start-page: 1504 year: 2011 ident: 10.1016/j.spmi.2018.09.012_bib15 article-title: CMOS-compatible vertical-silicon-nanowire gate-all-around p-type tunneling FETs with ≤ 50-mV/decade subthreshold swing publication-title: IEEE Electron. Device Lett. doi: 10.1109/LED.2011.2165331 – volume: 60 issue: 3 year: 2013 ident: 10.1016/j.spmi.2018.09.012_bib18 article-title: High-performance silicon nanotube tunneling FET for ultralow-power logic applications publication-title: IEEE Trans. Electron. Dev. doi: 10.1109/TED.2013.2243151 – volume: 30 issue: 7 year: 2009 ident: 10.1016/j.spmi.2018.09.012_bib17 article-title: Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires publication-title: IEEE Electron. Device Lett. doi: 10.1109/LED.2009.2021079 – ident: 10.1016/j.spmi.2018.09.012_bib5 – volume: 28 start-page: 743 issue: 8 year: 2007 ident: 10.1016/j.spmi.2018.09.012_bib7 article-title: Tunneling field-effect transistors with subthreshold swing less than 60mV/dec publication-title: IEEE Electron. Device Lett. doi: 10.1109/LED.2007.901273 – volume: 29 start-page: 1398 year: 2008 ident: 10.1016/j.spmi.2018.09.012_bib13 article-title: Complementary silicon-based heterostructure tunnel-FETs with high tunnel rates publication-title: IEEE Electron. Device Lett. doi: 10.1109/LED.2008.2007599 – volume: 104 year: 2008 ident: 10.1016/j.spmi.2018.09.012_bib12 article-title: Boosting the on-current of a n-channel nanowire tunnel field-effect publication-title: J. Appl. Phys. doi: 10.1063/1.2981088 – volume: 22 issue: 12 year: 2014 ident: 10.1016/j.spmi.2018.09.012_bib6 article-title: “Tunnel FETs for ultralow voltage digital VLSI circuits: Part I—device–Circuit interaction and evaluation at device level” publication-title: IEEE Trans. Very Large Scale Integr. Syst. doi: 10.1109/TVLSI.2013.2293135 – volume: 15 start-page: 850 year: 2016 ident: 10.1016/j.spmi.2018.09.012_bib9 article-title: Analog and RF performance of doping-less tunnel FETs with Si0.55Ge0.45 source publication-title: J. Comput. Electron. doi: 10.1007/s10825-016-0859-5 |
| SSID | ssj0009417 |
| Score | 2.1090002 |
| Snippet | In this research work, we have put forward Silicon based Nanotube structure with Dual Gate All around configuration. The proposed device has been compared with... |
| SourceID | crossref elsevier |
| SourceType | Enrichment Source Index Database Publisher |
| StartPage | 356 |
| SubjectTerms | Core and shell gates Dual-Gate All around Nanotube Nanowire TFET |
| Title | Design and performance analysis of Dual-Gate All around Core-Shell Nanotube TFET |
| URI | https://dx.doi.org/10.1016/j.spmi.2018.09.012 |
| Volume | 125 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwnV3NS8MwFA9jInoRnYrzY-TgTeL6kbbJcXSOqTiEbbBbSdoUJrMtW3f1b_clbf0A2cFLIeEFyu89Xl7TX94PodsgNj-PBFFeDB8oiaRECkaJk6YKIsQLXHPg9jLxx3P6tPAWLRQ2d2E0rbLO_VVON9m6nunXaPaL5bI_hc0Pym_Xh6C0vcDRbbcpDXSU33980zw4Naq72pho6_riTMXx2hTvS03vYqbXqe38vTn92HBGx-iorhTxoHqZE9RSWQcdhI1AWwftG_ZmvDlFr0PDw8AiS3DxfRMAxlXHEZyneLgVK6LPyvBgtcJireWUcJivFZlqLiiGNJuXW6nwbPQwO0NzeIZjUkslkNi1rJIknEspwBup9GTKpc2FZcfUTXwHJmUgtDy85StPUFv4CYuVYwvGbEtZDLzC3XPUzvJMXSDsgKs8x_IBMUVFwhnUJA5LOJUBZACZdJHdYBTFdR9xLWexihrC2FukcY00rpHFI8C1i-6-1hRVF42d1l4DffQrFiJI8zvWXf5z3RU6hBGvDlauUbtcb9UNlBql7JlY6qG9wePzePIJa6fR4A |
| linkProvider | Elsevier |
| linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwnV1LS8NAEB5qi9SLaFWszz14k6V5bZI9lmpp7QOhLfS27CYbqNS29PH_nc3DKkgPXgLZ7ED4ZpiZbL6ZAXgKovTnkaSaRfiBEiuPKhl61EkSjRbCAjc9cBsM_c7Ee5uyaQlaRS2MoVXmvj_z6am3zlcaOZqN1WzWGGHww_Tb9dEobRY4_hFUTHcqVoZKs9vrDPe9d7108K7ZT41AXjuT0bw2q8-ZYXiFabtT2_k7Pv2IOe0zOM2TRdLM3uccSnpRg2qrmNFWg-OUwBltLuD9JaViELmIyWpfDID3WdMRskzIy07OqTkuI835nMi1mahEWsu1piNDByXoaZfbndJk3H4dX8IEr60Ozacl0Mi1rC2NOVdKokISxVTClc2lZUeeG_sOLqpAmgnxlq-Z9Gzpx2GkHVuGoW1pK0TFcPcKyovlQl8DcVBbzLF8REx7MuYhpiVOGHNPBegEVFwHu8BIRHkrcTPRYi4KztiHMLgKg6uwuEBc6_D8LbPKGmkc3M0K6MUvcxDo6Q_I3fxT7hGqnfGgL_rdYe8WTvAJz85Z7qC8Xe_0PWYeW_WQW9YXr6DUkQ |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Design+and+performance+analysis+of+Dual-Gate+All+around+Core-Shell+Nanotube+TFET&rft.jtitle=Superlattices+and+microstructures&rft.au=Kumar%2C+Naveen&rft.au=Mushtaq%2C+Umar&rft.au=Amin%2C+S.+Intekhab&rft.au=Anand%2C+Sunny&rft.date=2019-01-01&rft.pub=Elsevier+Ltd&rft.issn=0749-6036&rft.eissn=1096-3677&rft.volume=125&rft.spage=356&rft.epage=364&rft_id=info:doi/10.1016%2Fj.spmi.2018.09.012&rft.externalDocID=S0749603618315726 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0749-6036&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0749-6036&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0749-6036&client=summon |