Kanban Feedback Control for Wafer Delay Regulation of Cluster Tools

In cluster tools widely used for semiconductor manufacturing, a wafer processed in a chamber should wait until a robot arm unloads it. Such wafer delays degrade the wafer quality due to residual chemicals and heat and hence cause quality variability and even failures. To prevent excessive wafer dela...

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Bibliographic Details
Published inIEEE transactions on automation science and engineering Vol. 22; pp. 6822 - 6838
Main Authors Roh, Dong-Hyun, Lee, Tae-Eog, Martinez, Claude
Format Journal Article
LanguageEnglish
Published IEEE 01.01.2025
Institute of Electrical and Electronics Engineers
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Summary:In cluster tools widely used for semiconductor manufacturing, a wafer processed in a chamber should wait until a robot arm unloads it. Such wafer delays degrade the wafer quality due to residual chemicals and heat and hence cause quality variability and even failures. To prevent excessive wafer delays and their variability for single-armed and dual-armed cluster tools, we propose a simple, effective, and robust feedback control method called Kanban feedback control(KFC) that postpones a wafer loading task until a completion event of an associated task triggers it. We model the feedback control design problem as a problem of adding a feedback path between a pair of transitions to regulate token delays at a place in a timed event graph model. We develop closed formulae for wafer delays of the tools with KFC. We prove that KFC minimizes the worst-case wafer delay. We also prove that KFC makes the tool have a unique 1-cyclic schedule with constant wafer delays and ensures strong stability that recovers the same 1-cyclic schedule and the constant wafer delay at each chamber in a few cycles after a time disruption. By experimentation, we verify that KFC significantly reduces wafer delays and robustly regulates wafer delays and even cycle times against persistent time variation and significant sporadic time disruptions. Note to Practitioners-As circuit widths shrink to a few nanometers and chip architectural complexity soars up due to FinFET, GAA, and high-rise circuit stack-ups, quality risk in wafer fabrication processes surges. Therefore, wafer delays within a chamber after processing can cause more serious quality variations and failures. We propose a simple, effective, and robust way of regulating wafer delays. It can significantly contribute to yield enhancement.
ISSN:1545-5955
1558-3783
DOI:10.1109/TASE.2024.3455253