A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 24; no. 4; pp. 1450 - 1459
• Main Authors: Lee, Taeho, Kim, Yong-Hun, Sim, Jaehyeong, Park, Jun-Seok, Kim, Lee-Sup
• Format: Journal Article
• Language: English
• Published: IEEE 01.04.2016
• Subjects: Bandwidth; Clocks; Data recovery; Delays; Delta-sigma modulator (DSM); Digital; digital clock and data recovery (CDR); digitally controlled oscillator (DCO); Dithering; high-speed serial link; hybrid dithering; Jitter; loop delay; Low pass filters; Modulators; Noise; Quantization (signal); resolution; time-dithered DSM (TDDSM); Transfer functions; Very large scale integration; digitally controlled oscillator (DCO); high-speed serial link; hybrid dithering; loop delay; time-dithered DSM (TDDSM); digital clock and data recovery (CDR); Delta–sigma modulator (DSM); resolution
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2015.2449866

A digital clock and data recovery (CDR) employing a time-dithered delta-sigma modulator (TDDSM) is presented. By enabling hybrid dithering of a sampling period as well as an output bit of the TDDSM, the proposed CDR enhances the resolution of digitally controlled oscillator, removes a low-pass filter in the integral path, and reduces jitter generation. Fabricated in a 65-nm CMOS process, the proposed CDR operates at 5-Gb/s data rate with BER <; 10 -12 for PRBS 31. The CDR consumes 13.32 mW at 5 Gb/s and achieves 2.14 and 29.7 ps of a long-term rms and peak-to-peak jitter, respectively.