Modeling and simulation analysis of SiGe heterojunction Double Gate Vertical t-shaped tunnel FET

This paper deals with a new 2-D analytical surface potential model for heterojunction SiGe Double Gate Vertical t-shaped Tunnel Field Effect transistor and contemplate the inherit property of TFET that is dual modulation effect. This influence explains the control on the surface potential of the bot...

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Bibliographic Details
Published inSuperlattices and microstructures Vol. 142; p. 106496
Main Authors Singh, Shailendra, Raj, Balwinder
Format Journal Article
LanguageEnglish
Published Elsevier Ltd 01.06.2020
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Summary:This paper deals with a new 2-D analytical surface potential model for heterojunction SiGe Double Gate Vertical t-shaped Tunnel Field Effect transistor and contemplate the inherit property of TFET that is dual modulation effect. This influence explains the control on the surface potential of the both biasing voltages at source and drain junctions that are used to measure the tunneling depletion widths. Therefore, the tunneling current uses the surface potential model as the basic for driving current model for the device. Parabolic approximation techniques are used to solve the equation of 2-D Poisson with the appropriate boundary conditions. We analyze the dependence of the surface potential profile on different parameters by varying the molefraction variation of SiGe material, gate source potential, drain source potential, gate oxide dielectric constant, gate oxide thickness, gate metal work function and different material used. Ultimately, we have the expression for the channel's surface potential along with tunneling current which have the accurate variation with the gate and drain biases. Efficiency of the proposed method has been confirmed by demonstrating the analytical results agreement with the TCAD simulation results. •A new 2-D analytical surface potential model for heterojunction SiGe Double-Gate Vertical t-shaped Tunnel Field Effect transistor (DG V t-TFET) has been presented.•By solving Poisson's equation, potential of gate-bias and drain bias have been calculated with imposed SiGe layer and then, current has been estimated.•The Kane's Model is used for calculating the tunneling generation rate to derive the drain current.•Ultimately, we have a new expression for the surface potential of the channel (C) which has the exact variation with the drain and gate biases.•Introduction to the 10 nm Silicon germanium layer between the source-channel tunneling junction makes aggressive improvement to the surface potential characteristics like gate oxide dielectric constant, gate oxide thickness, gate metal work function etc.
ISSN:0749-6036
1096-3677
DOI:10.1016/j.spmi.2020.106496