An automated FPGA real-time simulator for power electronics and power systems electromagnetic transient applications

•An automated FPGA-based real-time electromagnetic transients simulator is presented.•It is tailored to reproduce the behavior of power electronics and power systems circuits.•It is based on FAMNM with the optimal selection of the switch conductance value.•Parallel architecture, together with the ef...

Full description

Saved in:
Bibliographic Details
Published inElectric power systems research Vol. 141; pp. 147 - 156
Main Authors Razzaghi, R., Mitjans, M., Rachidi, F., Paolone, M.
Format Journal Article
LanguageEnglish
Published Elsevier B.V 01.12.2016
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:•An automated FPGA-based real-time electromagnetic transients simulator is presented.•It is tailored to reproduce the behavior of power electronics and power systems circuits.•It is based on FAMNM with the optimal selection of the switch conductance value.•Parallel architecture, together with the efficient sparse matrix multiplier are used.•The performances are validated by using both offline simulations and HIL tests. The paper presents an automated FPGA-based real-time electromagnetic transients simulator for power electronics and power systems applications. The simulator features an automated procedure enabling its straightforward applications to different topologies by avoiding the need of complex FPGA programming. The proposed solver integrates: (i) the Modified Augmented Nodal Analysis (MANA) method, (ii) the Fixed Admittance Matrix Nodal Method (FAMNM), (iii) the optimal selection of the switch conductance parameter, and (iv) efficient sparse matrix-to-vector multiplier. The simulator is able to accurately reproduce, in real-time, electromagnetic transients taking place in power electronics devices together with electromagnetic waves propagating in transmission lines. The peculiar structure of the MANA-FAMNM solver enables to reach extremely low integration time steps and avoids the need to redesign the FPGA code. The results of the proposed simulator are validated by dedicated comparisons with off-line EMTP-RV simulations and a hardware-in-the-loop (HIL) test for a three-phase two-level inverter and a three-phase power network.
ISSN:0378-7796
1873-2046
DOI:10.1016/j.epsr.2016.07.022