Exploratory study of a novel low occupancy vertex detector architecture based on high precision timing for high luminosity particle colliders

• Published in: Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment Vol. 857; pp. 31 - 41
• Main Authors: Orel, Peter, Varner, Gary S., Niknejadi, Pardis
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 11.06.2017
• Subjects: Electronic detector readout concepts (solid-state); Front-end electronics for detector readout; Si microstrip and pad detectors; Front-end electronics for detector readout; Si microstrip and pad detectors; Electronic detector readout concepts (solid-state)
• ISSN: 0168-9002; 1872-9576
• DOI: 10.1016/j.nima.2017.03.023

Vertex detectors provide space–time coordinates for the traversing charged particle decay products closest to the interaction point. Resolving these increasingly intense particle fluences at high luminosity particle colliders, such as SuperKEKB, is an ever growing challenge. This results in a non-negligible occupancy of the vertex detector using existing low material budget techniques. Consequently, new approaches are being studied that meet the vertexing requirements while lowering the occupancy. In this paper, we introduce a novel vertex detector architecture. Its design relies on an asynchronous digital pixel matrix in combination with a readout based on high precision time-of-flight measurement. Denoted the Timing Vertex Detector (TVD), it consists of a binary pixel array, a transmission line for signal collection, and a readout ASIC. The TVD aims to have a spatial resolution comparable to the existing Belle2 vertex detector. At the same time it offers a reduced occupancy by a factor of ten while decreasing the channel count by almost three orders of magnitude. Consequently, reducing the event size from about 1MB/event to about 5.9kB/event.