A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access time

• Published in: International journal of electronics and communications Vol. 162; p. 154565
• Main Authors: Sachdeva, Ashish, Kumar, Deepak, Abbasian, Erfan
• Format: Journal Article
• Language: English
• Published: Elsevier GmbH 01.04.2023
• Subjects: CNTFET; Delay; Low-power; Stability; Stability; CNTFET; Low-power; Delay
• ISSN: 1434-8411; 1618-0399
• DOI: 10.1016/j.aeue.2023.154565

Carbon nanotube field effect transistor (CNTFET) is swiftly becoming an alternative to conventional CMOS transistors due to superior transport properties, improved current handling characteristics, and better gate control. This work presents a new Carbon nanotube field effect transistor (CNTFET) based low power, stable static random access memory (SRAM) cell design with reduced write delay. The proposed eight-transistor (8T) CNTFET-based SRAM cell improves read/write static noise margin by 1.98×/1.25×, respectively, at 0.3 V compared to conventional 6T SRAM that uses similar CNTFET parameters. The write access time and leakage power of the proposed cell are improved by 1.90× and 2.14×, respectively, compared to the conventional 6T design. The proposed design parameters are also compared with two already presented 8T SRAM cells. The simulation is performed with the Cadence Virtuoso using the Stanford University 32 nm CNTFET Verilog model.