Allocation of multiport memories in data path synthesis

An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be ap...

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Published inIEEE transactions on computer-aided design of integrated circuits and systems Vol. 7; no. 4; pp. 536 - 540
Main Authors Balakrishnan, M., Majumdar, A.K., Banerji, D.K., Linders, J.G., Majithia, J.C.
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.04.1988
Institute of Electrical and Electronics Engineers
Subjects
Applied sciences
Bridges
Councils
Design automation
Digital systems
Electronics
Exact sciences and technology
Hardware design languages
Information science
Merging
Registers
Silicon compiler
Space exploration
Storage and reproduction of information
System architecture
Interconnection
Memory
Minimization
Bus(channel)
Storage allocation
Algorithm
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Summary:An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be applied to select the optimum number of buses in a multibus architecture. The method is illustrated with an example.< >
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0278-0070
1937-4151
DOI:10.1109/43.3188