Allocation of multiport memories in data path synthesis
An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be ap...
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Published in | IEEE transactions on computer-aided design of integrated circuits and systems Vol. 7; no. 4; pp. 536 - 540 |
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Main Authors | , , , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.04.1988
Institute of Electrical and Electronics Engineers |
Subjects | |
Online Access | Get full text |
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Summary: | An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be applied to select the optimum number of buses in a multibus architecture. The method is illustrated with an example.< > |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0278-0070 1937-4151 |
DOI: | 10.1109/43.3188 |