High performance HITA based Binary Edward Curve Crypto processor for FPGA platforms

• Published in: Journal of parallel and distributed computing Vol. 178; pp. 56 - 68
• Main Authors: Kalaiarasi, M., Venkatasubramani, V.R., Manikandan, M.S.K., Rajaram, S.
• Format: Journal Article
• Language: English
• Published: Elsevier Inc 01.08.2023
• Subjects: Edward curve cryptoprocessor; Elliptic Curve Cryptography (ECC); Field Programmable Gate Array (FPGA); Finite field; Finite field; Field Programmable Gate Array (FPGA); Elliptic Curve Cryptography (ECC); Edward curve cryptoprocessor
• ISSN: 0743-7315; 1096-0848
• DOI: 10.1016/j.jpdc.2023.03.008

In an embedded and resource-constrained environment, Elliptic Curve Cryptography (ECC) has been noted as an efficient and suitable methodology for achieving information security via public-key cryptography. However, the drawback of ECC is its lack of unifiedness in point operation that makes it prone to side-channel attack. Also, ECC does not satisfy the completeness property due to which the addition formula is not defined for all the pairs of input points. Edward curve, with its unified addition law and completeness property, proved to be the answer to aforementioned flaws. High throughput while maintaining low resource is a key issue for elliptic curve cryptography (ECC) hardware implementations in many applications. This paper presents the implementation of a Binary Edward curve Crypto processor over GF(2233) for FPGA platforms. The architecture is modified to perform scalar multiplication in a parallel manner using two hybrid Karatsuba field multipliers. Field inversion being one of the most tedious operations while reconversion, is also performed in a parallel manner using an efficient Hex Itoh-Tsujii inversion algorithm. The hardware resources are shared for performing point operations and inversion. Exploiting parallelism in point and inversion operations has resulted in reduction of the clock cycles consumed and the resultant architecture is more efficient in terms of throughput over area. The design takes 0.038 ms on Xilinx Virtex-4 and 0.031 ms on Virtex-7 FPGA platforms to perform a 233-bit point multiplication operation. It takes 73.57%, 13.71%, 14.76% and 48.76% more efficient than existing scalar multiplication with BEC. This proposed scalable, side-channel attack resilient design outperforms the existing techniques with respect to throughput over area. •The parallelism in BEC is done with two modular hybrid Karatsuba multiplier.•Inversion in reconversion is done with new Hex-Itoh Tsujii inversion algorithm (HITA).•Point operation and HITA uses the same resources with reduced clock cycles.•This architecture is designed for FPGA platforms yielding high throughput and area-time performance.