Design for Testability Features of Godson-3 Multicore Microprocessor

This paper describes the design for testability (DFT) challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar (SMOC) on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design...

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Bibliographic Details
Published inJournal of computer science and technology Vol. 26; no. 2; pp. 302 - 313
Main Authors Qi, Zi-Chu, Liu, Hui, Li, Xiang-Ku, Hu, Wei-Wu
Format Journal Article
LanguageEnglish
Published Boston Springer US 01.03.2011
Springer Nature B.V
Subjects
Analysis
Artificial Intelligence
Clocks
Clocks & watches
Collars
Compression tests
Computer Science
Correlation
Data Structures and Information Theory
Density functional theory
Design
Functional testing
Information Systems Applications (incl.Internet)
Low speed
Microprocessors
Partitions
Power management
Product design
R&D
Regular Paper
Research & development
Science
Software Engineering
Studies
Test times
Testability
Testing time
Theory of Computation
Transistors
low power test
TAM (test access mechanism)
multicore processor
DFT (design for testability)
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Summary:This paper describes the design for testability (DFT) challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar (SMOC) on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism (TAM) is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
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ISSN:1000-9000
1860-4749
DOI:10.1007/s11390-011-9437-2