Disordered wall arrays by photo-assisted electrochemical etching in n-type silicon

The fabrication of ordered, high aspect-ratio microstructures in silicon by use of photo-assisted electrochemical etching is an important technology, where voltage and current density are significant factors. In this paper, disordered walls appear in 5-inch n-type silicon wafers when a large current...

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Bibliographic Details
Published inJournal of semiconductors Vol. 37; no. 10; pp. 92 - 96
Main Author 雷耀虎 赵志刚 郭金川 李冀 牛憨笨
Format Journal Article
LanguageEnglish
Published 01.10.2016
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Summary:The fabrication of ordered, high aspect-ratio microstructures in silicon by use of photo-assisted electrochemical etching is an important technology, where voltage and current density are significant factors. In this paper, disordered walls appear in 5-inch n-type silicon wafers when a large current density is used. Based on the theory of space charge region, these disordered walls are caused by the contradiction between the protection from dissolution by a high applied voltage and the dissolution by a high current density. To verify this point, wall arrays were fabricated at different applied voltages and current densities. Moreover, the critical voltage was kept constant and different current densities were applied to obtain conditions for avoiding disordered walls and achieving uniform wall arrays. Finally, a wall array with a period of 5.6 μm and a depth of 55 μm was achieved at an applied voltage of 3 V and a monotonically increasing current density ranging from 22.9 to 24.5 mA/cm2.
Bibliography:Lei Yaohu;Zhao Zhigang;Guo Jinchuan;Li Ji;Niu Hanben;Key Laboratory of Optoelectronic Devices and Systems of Ministry of Education and Guangdong Province, College of Optoelectronic Engineering, Shenzhen University
11-5781/TN
ISSN:1674-4926
DOI:10.1088/1674-4926/37/10/106001