Approach to partially self-checking combinational circuits design

• Published in: Microelectronics Vol. 35; no. 12; pp. 945 - 952
• Main Authors: Djordjevic, Goran Lj, Stojcev, Mile K., Stankovic, Tatjana R.
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.12.2004
• Subjects: Approximation of logic functions; Concurrent error detection; Fault tolerance; Partially self-checking circuits; Partially self-checking circuits; Fault tolerance; Approximation of logic functions; Concurrent error detection
• ISSN: 1879-2391; 1879-2391
• DOI: 10.1016/j.mejo.2004.07.007

This paper presents a cost-effective, non-intrusive technique of partially self-checking combinational circuits design. The proposed technique is similar to duplication with comparison, wherein duplicated function module and comparator act as a function checker that detects any erroneous response of the original function module. However, instead of realizing checker with full error-detection capability, we select a subset of erroneous responses to implement partial, but simplified function checker. A heuristic procedure that tries to find the optimal sum-of-product expression for partial function checker that minimizes its area while providing specified error coverage is described here. Effectiveness of the technique is evaluated on a set of MCNC 91 benchmark combinational circuits.