Proof-Carrying Hardware-Based Information Flow Tracking in Analog/Mixed-Signal Designs

• Published in: IEEE journal on emerging and selected topics in circuits and systems Vol. 11; no. 2; pp. 415 - 427
• Main Authors: Bidmeshki, Mohammad Mahdi, Antonopoulos, Angelos, Makris, Yiorgos
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.06.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog circuits; analog/mixed-signal design; Channels; Circuit design; Circuits; Circuits and systems; Design modifications; Domains; Electronic systems; Hardware; Hardware description languages; Hardware design languages; hardware Trojans; hardware trust; Information flow; Information flow tracking; information leakage; Leakage; Methodology; Security; Software; Tracking; Transistors; Trojan horses
• ISSN: 2156-3357; 2156-3365
• DOI: 10.1109/JETCAS.2021.3075098

Information flow tracking (IFT) is a widely used methodology for ensuring data confidentiality and/or integrity in electronic systems and many such methods have been developed at various software or hardware description levels. Among them, Proof-Carrying Hardware Intellectual Property (PCHIP) introduced an IFT methodology for digital hardware designs described in hardware description languages (HDLs). However, it is not only the digital domain that suffers from the risk of inadvertent information leakage. Indeed, analog signals originating from sources of sensitive information such as biometric sensors, as well as analog circuit outputs could also carry confidential information. Moreover, analog circuits are equally susceptible as their digital counterparts to malicious modifications, known as hardware Trojans, which could introduce covert channels for leaking such confidential information. Furthermore, in analog/mixed-signal circuits, such information leakage channels may cross the analog/digital or digital/analog interface, making their detection even harder and, thereby, intensifying this security concern. As a solution, we introduce a PCHIP-based methodology which enables systematic formal evaluation of information flow policies in analog/mixed-signal designs. This solution can reason on analog designs described at the transistor-level or at the block-level, where an abstract model of the analog circuit is considered. Additionally, it can handle analog circuit models developed in Verilog-A or Verilog-AMS, thereby enabling the use of circuit models developed in these HDLs for IFT purposes. By integrating IFT across the digital and analog domains, the proposed solution is able to detect sensitive data leakage from the digital domain to the analog domain and vice-versa, without requiring any modification of the current analog/mixed-signal circuit design flow.