Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM

• Published in: IEEE journal on emerging and selected topics in circuits and systems Vol. 6; no. 3; pp. 364 - 372
• Main Authors: Nomura, Takao, Mori, Ryo, Takayanagi, Koji, Fukuoka, Kazuki, Nii, Koji
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.09.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitance; Delays; Electronics industry; Electrostatic discharges; Fully digital noise monitor; impedance optimization; Monitoring; pre-bonding test; Random access memory; simultaneous switching noise; Stacking; Switches; thermal aware memory control; through silicon via (TSV); wide I/O DRAM
• ISSN: 2156-3357; 2156-3365
• DOI: 10.1109/JETCAS.2016.2547719

Design techniques for 3-D SoC stacked with a Wide I/O DRAM with through silicon via (TSV) technology were developed. Some of the developed techniques were applied to design a Wide I/O DRAM controller chip. Micro-I/O cells and area efficient decoupling capacitor cells are implemented in between the fine pitch TSV array. Test circuitry for pre-bonding TSV tests are embedded in the micro-I/O cells with small area overhead. In order to reduce V min degradation induced by 512 DQs simultaneous switching noise, we introduce a package-board impedance optimization scheme utilizing a full digital noise monitor. We also developed a thermal aware memory control technique to adaptively change the refresh rates per channel, which are hot due to SoC hotspots. We achieved 12.8 GB/s operation, while I/O power was reduced by 89% compared to LPDDR3.