Design and fabrication results of Z-gate layout MOSFETs for radiation hardness integrated circuit

Abstract A Z-gate layout MOSFET (ZLT) is expected to reduce the total ionizing dose effects which occur in the shallow trench isolation layer made of oxide. To verify the ZLT’s merit, the ZLT was designed and fabricated with the 0.18 μ m standard CMOS technology. The ZLT was irradiated with 60 Co γ...

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Bibliographic Details
Published inJapanese Journal of Applied Physics Vol. 62; no. SC; p. SC1045
Main Authors Kuroki, Kaito, Kimura, Arisa, Hirakawa, Kenji, Iwase, Masayuki, Ogasawara, Munehiro, Yoda, Takashi, Ishihara, Noboru, Ito, Hiroyuki
Format Journal Article
LanguageEnglish
Published Tokyo IOP Publishing 01.04.2023
Japanese Journal of Applied Physics
Subjects
CMOS
Current voltage characteristics
Gamma rays
integrated circuit
Integrated circuits
Layouts
MOSFETs
radiation hardness
Threshold voltage
total ionizing dose (TID) effect
Z-gate layout MOSFET
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Summary:Abstract A Z-gate layout MOSFET (ZLT) is expected to reduce the total ionizing dose effects which occur in the shallow trench isolation layer made of oxide. To verify the ZLT’s merit, the ZLT was designed and fabricated with the 0.18 μ m standard CMOS technology. The ZLT was irradiated with 60 Co γ -rays up to 10 Mrad, and its I – V characteristic fluctuation was compared with that of a standard straight gate layout MOSFET (SLT). As a result, it was confirmed that the Z-gate can suppress off-current fluctuations by 1/5, on-current fluctuations by 1/2 and threshold voltage fluctuations by 1/6 compared with the SLT. Since the size penalty of the ZLT is small, it is possible to improve the radiation hardness of the CMOS LSI circuit by just replacing SLTs with ZLTs.
Bibliography:JJAP-S1103019.R1
ISSN:0021-4922
1347-4065
DOI:10.35848/1347-4065/acb0d7