Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 21; no. 7; pp. 1337 - 1341
• Main Authors: Hwang, Seong-In, Lee, Hanho
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.07.2013; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Belief propagation; block-circulant (BC) parity-check matrix; Circuit properties; Decoding; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; layered decoding; Logic gates; low-density parity-check (LDPC) codes; Parity check codes; Signal convertors; Sparse matrices; Switching, multiplexing, switched capacity circuits; Throughput; Vectors; Reed Solomon code; Performance evaluation; High performance; block-circulant (BC) parity-check matrix; Coding circuit; Data transmission; Iterative method; Decoding circuit; Decoding; low-density parity-check (LDPC) codes; Coding; layered decoding; Parity check codes; Selector switch; Parity check; Belief propagation
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2012.2210452

This brief presents a method for constructing block-circulant (BC) Reed-Solomon-based low-density parity-check (RS-LDPC) codes and an efficient decoder design. The proposed construction method results in a BC form of a parity-check matrix from a random parity-check matrix for RS-LDPC codes. A decoder architecture and switch network for BC-RS-LDPC code are then developed based on the new BC parity-check matrix. Thus, an efficient decoder architecture dedicated to a promising class of high-performance BC-RS-LDPC codes is presented for the first time. Moreover, a (2048, 1723) BC-RS-LDPC decoder architecture is designed to demonstrate the efficiency of the presented techniques. Synthesis results show that the proposed decoder requires 1.3-M gates and can operate at 450 MHz to achieve a data throughput of 41 Gb/s with eight iterations.