IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 21; no. 7; pp. 1333 - 1337
• Main Authors: Li, Katherine Shu-Min, Yi-Yu Liao
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.07.2013; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Circuit faults; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuit interconnections; Integrated circuits; Interconnect; multicore; Multicore processing; multilevel framework; oscillation test; Oscillators; Parallel processing; Partitioning algorithms; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; system-on-chips (SoCs); test parallelism; Performance evaluation; Interconnect; System on a chip; multilevel framework; Oscillation method; Algorithm; multicore; oscillation test; test parallelism; Interconnection; Integrated circuit; Test method; Parallelism; system-on-chips (SoCs); Diagnostic aid; Multilevel system
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2012.2210451

On-chip interconnect structures become much more complicated and dominate system performance in multicore system-on-chips. Oscillation ring (OR) test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that both 100% fault coverage and the optimum diagnosis resolution for various fault models are achievable. The cost of OR test is decided by the number of test sessions required to form all the rings. Previous ring generation algorithm tries to generate long rings that usually cannot be put into the same test session, and thus the number of test sessions is not necessarily smaller. In this brief, we study techniques to generate rings that can be tested concurrently, so that the overall test time can be reduced significantly.