Analysis of asynchronous binary arbitration on digital transmission-line busses

A common misconception is that asynchronous binary arbitration settles in at most four units of bus-propagation delay, irrelevant of the number of arbitration bus lines. The author disproves this conjecture by presenting an arrangement of modules on m bus lines, for which binary arbitration requires...

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Bibliographic Details
Published inIEEE transactions on computers Vol. 43; no. 4; pp. 484 - 489
Main Author Kipnis, S.
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.04.1994
Institute of Electrical and Electronics Engineers
Subjects
Applied sciences
Computer science
Computer science; control theory; systems
Computer systems and distributed systems. User interface
Degradation
Delay effects
Delay lines
Exact sciences and technology
Fastbus
Power system transients
Propagation delay
Signal analysis
Software
System performance
Transmission lines
Asynchronous binary arbibration
Bus-propagation delay
Arbitration time
Distributed system
Digital transmission line
Arbitration bus
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Summary:A common misconception is that asynchronous binary arbitration settles in at most four units of bus-propagation delay, irrelevant of the number of arbitration bus lines. The author disproves this conjecture by presenting an arrangement of modules on m bus lines, for which binary arbitration requires /spl lsqb/m/2/spl rsqb/ units of bus-propagation delay to settle. He also proves that for any arrangement of modules on m bus lines, binary arbitration settles in at most /spl lsqb/m/2/spl rsqb/+2 units of bus-propagation delay.< >
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9340
1557-9956
DOI:10.1109/12.278487