A virtual channel router for on-chip networks

This paper proposes an architecture of a virtual channel router for an on-chip network. The router has simple dynamic arbitration which is deterministic and fair. We show that the size of the proposed router is reduced by 49% and the speed increases 1.4 times compared to a conventional virtual chann...

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Bibliographic Details
Published inIEEE International SOC Conference, 2004. Proceedings pp. 289 - 293
Main Authors Kavaldjiev, N., Smit, G.J.M., Jansen, P.G.
Format Conference Proceeding
LanguageEnglish
Published Piscataway NJ IEEE 2004
Subjects
Application specific integrated circuits
Applied sciences
Bandwidth
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Hardware
Input-output equipment
Integrated circuit interconnections
Integrated circuits
Multiprocessor interconnection networks
Network-on-a-chip
Quality of service
Routing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Streaming media
System-on-a-chip
Telecommunication traffic
Interconnection network
Network architecture
Router
System on a chip
Deterministic approach
Integrated circuit
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Summary:This paper proposes an architecture of a virtual channel router for an on-chip network. The router has simple dynamic arbitration which is deterministic and fair. We show that the size of the proposed router is reduced by 49% and the speed increases 1.4 times compared to a conventional virtual channel router.
ISBN:9780780384453
0780384458
DOI:10.1109/SOCC.2004.1362438