A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 70; no. 6; pp. 1816 - 1820
• Main Authors: Xiao, Kanglin, Cui, Xiaoxin, Qiao, Xin, Song, Jiahao, Luo, Haoyang, Wang, Xin'an, Wang, Yuan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog to digital converters; Attenuators; capacitive coupling; Capacitors; Computation; Computer architecture; computing-in-memory (CIM); Energy efficiency; hierarchical capacity attenuator; input sparsity; Random access memory; SRAM; Static random access memory; Switches; Throughput; Voltage
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2023.3234620

Computing-in-memory (CIM) is an emerging approach for alleviating the Von-Neumann bottleneck of latency and energy overheads, and improving energy efficiency and throughput. In this brief, we present a novel CIM macro aimed at improving the energy efficiency and throughput of edge devices when running 4b multiply-and-accumulate (MAC) operations. The proposed architecture uses (1) a customized 9T1C bit-cell in charge-domain computation for sensing margin improvement and compact design; (2) a hierarchical capacity attenuator for 4b weight accumulation without complicated controlling switches and signals for throughput improvement; (3) an input sparsity-sensing-based flash analog-to-digital converters readout scheme to improve energy efficiency and throughput. Fabricated in 28nm CMOS technology, the proposed 32Kb SRAM CIM macro demonstrates an average energy efficiency of 646.6 TOPS/W (normalized to 4b/4b input/weight) and a throughput of 1638.4 GOPS while achieving 84.89% classification accuracy on the CIFAR-10 dataset at 4b precision in inputs and weights.