A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 31; no. 11; pp. 1700 - 1712
• Main Authors: Xiao, Rui, Zhang, Yewei, Wang, Bo, Xu, Yanfeng, Fan, Jicong, Shen, Haibin, Huang, Kejie
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Artificial intelligence; Canonical signed digit; charge redistribution integrator; Common Information Model (computing); Common Information Model (electricity); Computation; Data transfer (computers); Energy efficiency; in-memory computing; Memory tasks; Neurons; Nonvolatile memory; nonvolatile memory (NVM); Power consumption; Power demand; Power management; radix-4 booth recoding; Resistance; Storage units
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2023.3306376

Data transfer between the processing and storage units has become a significant bottleneck in modern von Neumann computing systems for artificial intelligence (AI) tasks. Computing in memory (CIM) has emerged as a promising candidate for lowering latency and power consumption. However, the conventional analog CIM schemes are suffering from reliability issues, which may significantly degenerate the accuracy of the computation. Recently, digitized input data and weights have been utilized for high-reliable in-memory computing. However, the properties of the digital memory and input data are not fully utilized. This article presents a novel low-power CIM scheme to further reduce the power consumption by using a modified radix-4 (M-RD4) booth algorithm at the input and a modified canonical signed digit (M-CSD) for the network weights. The simulation results show that M-RD4 and M-CSD reduce the number of nonzero activation bits by 24.2% and the number of nonzero weight bits by 36.0% in AlexNet, respectively. The power consumption can be reduced by 41.6% on average. The computing-power ratio at the fixed-point 8 bit is 60.7 tera operations per second per watt (TOPS/W), and the density is 0.177 TOPS/mm2.