High-Speed Smart Camera with High Resolution

• Published in: EURASIP Journal on Embedded Systems Vol. 2007; no. 1; pp. 1 - 16
• Main Authors: Mosqueron, R., Dubois, J., Paindavoine, M.
• Format: Journal Article
• Language: English
• Published: SpringerOpen 2007
• Subjects: Computer Science; Embedded Systems; smart camera; embedded processing; real-time processing
• ISSN: 1687-3955; 1687-3963
• DOI: 10.1155/2007/24163

High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has enabled the development of high-speed video cameras offering digital outputs, readout flexibility, and lower manufacturing costs. In this paper, we propose a high-speed smart camera based on a CMOS sensor with embedded processing. Two types of algorithms have been implemented. A compression algorithm, specific to high-speed imaging constraints, has been implemented. This implementation allows to reduce the large data flow (6.55 Gbps) and to propose a transfer on a serial output link (USB 2.0). The second type of algorithm is dedicated to feature extraction such as edge detection, markers extraction, or image analysis, wavelet analysis, and object tracking. These image processing algorithms have been implemented into an FPGA embedded inside the camera. These implementations are low-cost in terms of hardware resources. This FPGA technology allows us to process in real time 500 images per second with a 1280x1024 resolution. This camera system is a reconfigurable platform, other image processing algorithms can be implemented.