FPGA-based Acceleration of Davidon-Fletcher-Powell Quasi-Newton Optimization Method

• Published in: Transactions of Tianjin University Vol. 22; no. 5; pp. 381 - 387
• Main Author: 刘强;桑若愚;张齐军
• Format: Journal Article
• Language: English
• Published: Tianjin Tianjin University 01.10.2016; Springer Nature B.V
• Subjects: Acceleration; array; Engineering; field; Field programmable gate arrays; gate; Hardware; Humanities and Social Sciences; Mechanical Engineering; method; multidisciplinary; programmable; Quasi Newton methods; quasi-Newton; Science; field programmable gate array; hardware acceleration; quasi-Newton method
• ISSN: 1006-4982; 1995-8196
• DOI: 10.1007/s12209-016-2870-0

Quasi-Newton methods are the most widely used methods to find local maxima and minima of functions in various engineering practices. However, they involve a large amount of matrix and vector operations, which are computationally intensive and require a long processing time. Recently, with the increasing density and arithmetic cores, field programmable gate array (FPGA) has become an attractive alternative to the acceleration of scientific computation. This paper aims to accelerate Davidon-Fletcher-Powell quasi-Newton (DFP-QN) method by proposing a customized and pipelined hardware implementation on FPGAs. Experimental results demonstrate that compared with a software implementation, a speed-up of up to 17 times can be achieved by the proposed hardware implementation.