The Adiabatically Driven StrongARM Comparator

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 66; no. 12; pp. 1957 - 1961
• Main Authors: Filippini, Leo, Taskin, Baris
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: ADC; Adiabatic; adiabatic comparator; Adiabatic flow; adiabatic logic; Analog circuits; Capacitance; charge recovery circuits; charge recovery comparator; charge recovery logic; Circuits and systems; Clocks; Comparator; Computer simulation; Digital electronics; Discharges (electric); Electric power supplies; Energy consumption; Principles; Regeneration; Sine waves; Transistors
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2019.2896597

Adiabatic logic, also known as charge recovery logic, is subject to active research in the field of low-energy computation. Although the principles of adiabatic operation are well understood in digital circuits, analog and mixed-signal circuit implementations are largely unexplored. This brief shows that the strongARM comparator can take advantage of adiabatic principles by: 1) being powered by a sine-wave, the power-clock, rather than the conventional dc power supply, V DD and 2) using an adiabatic buffer as the output stage, rather than an SR-latch. Post-layout simulations in a 65-nm technology show that the adiabatically driven strongARM has similar characteristics to the traditional strongARM: +2% noise, +0.1% input offset voltage, and the same regeneration time-constant, while only consuming between 28% and 55% of the energy of the traditional strongARM, in the typical case.