A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 65; no. 9; pp. 1154 - 1158
• Main Authors: Kim, Si-Nai, Kim, Woo-Cheol, Seo, Min-Jae, Ryu, Seung-Tak
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Clocks; CMOS; DAC; Digital to analog conversion; Digital to analog converters; Digital-analog conversion; Gates (circuits); high-speed interface; Leakage current; Leakage currents; Linearity; Logic circuits; Power consumption; Power demand; Power supplies; Steering; Switches; time-interleaving; Timing
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2018.2809965

A 6-bit 20 GS/s two-channel time-interleaved current-steering digital-to-analog converter (DAC) with compact full-binary sub-DACs is presented. Optimally adjusted transition timings between the input data and the interleaving clock minimize glitches by the time-interleaving switches and enhance the high-frequency linearity. In order to prevent static linearity degradation by the leakage current through the time-interleaving switches, the relationship between the output current and the leakage current is analyzed. The proposed DAC architecture and the pseudo-differential logic gates for the high-speed data interface reduce the circuit complexity as well as the power consumption. The prototype 6-bit 20 GS/s DAC, fabricated in a 65-nm CMOS process, achieves a spurious-free dynamic range of 35.1 dB up to the Nyquist input, and consumes 136 mW given a 1.2-V power supply.