A Low-Power Motion Estimation Architecture for HEVC Based on a New Sum of Absolute Difference Computation

• Published in: IEEE transactions on circuits and systems for video technology Vol. 30; no. 1; pp. 243 - 255
• Main Authors: Jia, Luheng, Tsui, Chi-Ying, Au, Oscar C., Jia, Kebin
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Coders; Coding; Complexity; computation reuse; Computational complexity; Computer architecture; Electronic devices; Encoding; Hardware; HEVC; Integrated circuits; low-power; Mathematical analysis; Microsoft Windows; Motion estimation; Motion simulation; Power consumption; Power demand; SAD; Video compression
• ISSN: 1051-8215; 1558-2205
• DOI: 10.1109/TCSVT.2018.2890204

High-efficiency video coding (HEVC) poses a considerable challenge to hardware implementation due to its complexity. Mobile devices are powered by batteries that are limited in capacity. Therefore, reducing the power consumption arising from the implementation of sophisticated coding tools in HEVC is an especially important issue for mobile devices. In particular, motion estimation (ME) is the major contributor to the power consumption of the encoder and the calculation of the sum of absolute difference (SAD) for ME consumes more than 50% of the total ME power. In this paper, a low-power motion estimation VLSI architecture is proposed based on a novel method of calculating the SAD. By reusing the calculation, the computation complexity and, hence, the power consumption are reduced. A low-power systolic processing elements array and a novel memory hierarchy are developed, which enable real-time processing of 8K resolution video with only half of the power consumption when compared with the state-of-the-art design.