Gated Diode Investigation of Bias Temperature Instability in High- \kappa FinFETs

Bias temperature instability (BTI) in FinFET transistors was investigated by charge-pumping (CP) and gated-diode measurements using n + /p - /p + structures with the gate interface identical to that in SOI-FinFETs. The results show greatly improved sensitivity for gated diode measurements than for C...

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Bibliographic Details
Published inIEEE electron device letters Vol. 31; no. 7; pp. 653 - 655
Main Authors Young, Chadwin D, Neugroschel, Arnost, Matthews, Kenneth, Smith, Casey, Dawei Heh, Hokyung Park, Hussein, Muhammad M, Taylor, William, Bersuker, Gennadi
Format Journal Article
LanguageEnglish
Published IEEE 01.07.2010
Subjects
Bias
Bias temperature instability (BTI)
charge pumping
Charge pumps
Current measurement
DCIV
Density
Density measurement
Devices
Diodes
FinFET
FinFETs
Gates
hafnium
high- k
Information technology
Instability
Kinetic theory
Niobium compounds
Stability
Stress
Temperature sensors
Tin
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Summary:Bias temperature instability (BTI) in FinFET transistors was investigated by charge-pumping (CP) and gated-diode measurements using n + /p - /p + structures with the gate interface identical to that in SOI-FinFETs. The results show greatly improved sensitivity for gated diode measurements than for CP. The pre-stress interface trap density was found to be N IT ≅ 10 11 cm -2 for SiO 2 /2 nm-HfSiON/TiN/polySi-capped gate stacks, which is about one decade larger than in planar devices. The kinetics of ΔN IT (t) under negative bias stress conditions (NBTI) suggests N IT is generated by Si-H bond breaking. The mechanism for interface trap generation under positive bias stress conditions (PBTI) requires further investigation.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2010.2049635