Adaptive Spur Cancellation Technique in All-Digital Phase-Locked Loops

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 64; no. 11; pp. 1292 - 1296
• Main Authors: Avivi, Rotem, Kerner, Michael, Shumaker, Evgeny, Puma, Giuseppe Li, Sela, Tami, Sofer, Lidor, Horovitz, Gil
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive control; Chains; Clocks; CMOS; digital phase-locked loop (DPLL); Electronic devices; Frequency conversion; local oscillator (LO); Machine learning; Notch filters; Phase locked loops; Phase locked systems; Phase noise; spur cancelation; Voltage-controlled oscillators; Wireless communication; Wireless communications
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2017.2650782

The phenomenon of periodic phase errors (also known as spurs) in phase-locked loops (PLLs) is widely acknowledged and is responsible for posing considerable challenge on development of miniaturized wireless communication devices. The common approach employed today for spur mitigation calls for a digital notch filter within the receive chain, while there is no similar digital scheme for the transmit chain. In addition, this notch filter is not perfect and usually degrades the overall receiver sensitivity. This brief puts forward a novel idea, which is to cancel the spurs inside the PLL such that the local oscillator signal and consequently TX and RX antenna ports become spur-free. The technique is based on a least-mean squares algorithm that features a self-learning capability. The method has been silicon proven in a digital PLL of a transceiver radio test chip realized in a standard nanoscale CMOS technology.