Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 29; no. 5; pp. 973 - 984
• Main Authors: Lin, Jai-Ming, Deng, You-Lun, Yang, Ya-Chu, Chen, Jia-Jian, Lu, Po-Chen
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Data structures; Design hierarchy (DH); DH-HEMTs; Evolutionary algorithms; macro placement; Macros; mixed size; Partitioning algorithms; physical design; Placement; Routing; Simulated annealing; Simulated evolution; Simulation; Stitching; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2021.3057921

This article proposes a novel approach to handle macro placement. Previous works usually apply the simulated annealing (SA) algorithm to handle this problem. However, the SA-based approaches usually have difficulty in handling preplaced macros and require longer runtime. To resolve these problems, we propose a macro placement procedure based on the corner stitching data structure and then apply an efficient and effective simulated evolution algorithm to further refine placement results. In order to relieve local routing congestion, we propose to expand areas of movable macros according to the design hierarchy before applying the macro placement algorithm. Finally, we extend our macro placement methodology to consider dataflow constraint so that dataflow-related macros can be placed at close locations. The experimental results show that our approach obtains a better solution than a previous macro placement algorithm and a tool. Besides, placement quality can be further improved when the dataflow constraint is considered.