High-Performance Ternary Adder Using CNTFET

• Published in: IEEE transactions on nanotechnology Vol. 16; no. 3; pp. 368 - 374
• Main Authors: Sahoo, Subhendu Kumar, Akhilesh, Gangishetty, Sahoo, Rasmita, Muglikar, Manasi
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2017; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Adding circuits; Carbon nanotube; Carbon nanotube field effect transistor; Carbon nanotubes; Circuits; CNTFETs; Decoding; Delay; Field effect transistors; HSPICE; Inverters; Logic design; Logic gates; multiple-valued logic; Multivalued logic; Semiconductor devices; ternary half adder
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2017.2649548

Ternary logic is a promising alternative to the conventional binary logic in VLSI design as it provides the advantages of reduced interconnects, higher operating speeds, and smaller chip area. This paper presents a pair of circuits for implementing a ternary half adder using carbon nanotube field-effect transistors. The proposed designs combine both futuristic ternary and conventional binary logic design approach. One of the proposed circuits for ternary to binary decoder simplifies further circuit implementation and provides excellent delay and power advantages in data path circuit such as adder. These circuits have been extensively simulated using HSPICE to obtain power, delay, and power delay product. The circuit performances are compared with alternative designs reported in recent literature. One of the proposed ternary adders has been demonstrated power, power delay product improvement up to 63% and 66% respectively, with lesser transistor count. So, the use of these half adders in complex arithmetic circuits will be advantageous.