Parallel Branching of Two 2-DIMM Sections With Write-Direction Impedance Matching for an 8-Drop 6.4-Gb/s SDRAM Interface

• Published in: IEEE transactions on components, packaging, and manufacturing technology (2011) Vol. 9; no. 2; pp. 336 - 342
• Main Authors: Lee, Won-Cheol, Chae, Min-Kyun, Soh, Kyoung-Jae, Seo, Ensung, Sohn, Young-Soo, Park, Kwangil, Kim, Byungsub, Sim, Jae-Yoon, Park, Hong-June
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.02.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: DDR5; dual in-line memory module (DIMM); Dynamic random access memory; high-speed memory interface; Impedance matching; multidrop; Pins; Random access memory; Reflection; Resistors; SDRAM; Sockets; stub series terminated logic (SSTL); synchronous dynamic random access memory (SDRAM) channel; Transmission line measurements; Transmission lines
• ISSN: 2156-3950; 2156-3985
• DOI: 10.1109/TCPMT.2018.2869593

A parallel branching synchronous dynamic random access memory (SDRAM) channel with write-direction impedance matching (parallel branching with write-direction impedance matching (PBIM)) is proposed for an 8-drop 6.4-Gb/s SDRAM interface. The 8-drop PBIM channel consists of two parallel branches; each branch consists of a series connection of two dual in-line memory modules for a 4-drop configuration and the data (data pin) channel uses two kinds of transmission lines with characteristic impedances of 50 and <inline-formula> <tex-math notation="LaTeX">25~\Omega </tex-math></inline-formula> and a resistor on the motherboard. Measurements on the test setup show that the proposed 8-drop channel works at the DDR5 target data rate of 6.4 Gb/s in both write and read directions by using the same motherboard area as that of the stub series terminated logic channel and a bit-error-rate tester for transmitter and receiver.