DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 4; pp. 1030 - 1042
• Main Authors: Lin, Dave Y.-W., Wen, Charles H.-P.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Automotive electronics; Characterization; Computer architecture; Delays; design flow; Error reduction; Flip-flops; heavy ion; Heavy ions; Ions; Libraries; Microprocessors; Radiation hardening; Robustness; Safety critical; semiconductor device modeling; singleevent transient (SET); soft error; Soft errors; technology computer-aided design (TCAD) simulation
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2019.2962080

For the safety-critical applications such as biomedical and automobile electronics, the system failure induced by soft errors becomes a major issue of reliability. However, most of the commercial cell libraries do not include radiation-hardened components to build a safety-critical design. Therefore, a delay-adjustable D-flip-flop (DAD-FF) is proposed together with a design flow to construct a radiation-hardened system by automation. To enable such radiation-hardened design into the current design flow, DAD-FF is characterized as a general cell and compiled as a patch in the NanGate FreePDK45 bulk 45-nm open cell library, as an example. The experimental results show that DAD-FF is capable of reducing <inline-formula> <tex-math notation="LaTeX">1.3\times 10^{10}\text{X} </tex-math></inline-formula> soft errors with respect to the standard flip-flop (STD-FF) and resisting over 99.999997% strikes of heavy ions. Meanwhile, four radiation-hardened benchmark circuits are synthesized with DAD-FF cell, and further used to prove the effectiveness against soft errors compared to a prior work, built-in soft-error resilience (BISER), with 18% area and 40% timing improvement. To sum up, DAD-FF is elaborated from the modeling at the device-level to the validation at the system-level and exhibits its strong robustness to soft errors.