ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures

An asymmetric architecture is commonly used in modern embedded systems to reduce energy consumption. The systems tend to execute more applications in the energy-efficient core, which typically employs ultralow voltage (ULV) to save energy. However, caches become a reliability and performance barrier...

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Bibliographic Details
Published inIEEE transactions on very large scale integration (VLSI) systems Vol. 25; no. 12; pp. 3341 - 3354
Main Authors Wang, Po-Hao, Chien, Yung-Chen, Tsai, Shang-Jen, Lin, Xuan-Yu, Tanjung, Rizal, Lin, Yi-Sian, Syu, Shu-Wei, Lin, Tay-Jyi, Wang, Jinn-Shyan, Chen, Tien-Fu
Format Journal Article
LanguageEnglish
Published New York IEEE 01.12.2017
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Asymmetry
Cache memory
Computer architecture
Computer memory
Delays
Discharges (electric)
Electric potential
Embedded systems
Energy conservation
Energy consumption
low voltage
Random access memory
Reference systems
reliability
Static random access memory
system energy saving
timing discrepancy reducing
Transistors
Wearable technology
Workload
Workloads
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Summary:An asymmetric architecture is commonly used in modern embedded systems to reduce energy consumption. The systems tend to execute more applications in the energy-efficient core, which typically employs ultralow voltage (ULV) to save energy. However, caches become a reliability and performance barrier that limits the minimum operating voltage and blocks system performance in the ULV environment. The poor performance of an ultralow-voltage core causes most workload requirements to awaken and then execute on the host core, leading to high energy consumption. In this paper, we propose a ULV-Turbo cache based on a ULV-selective-ally 8T static random access memory (SRAM) that is able to perform reliable ultralow-voltage operation and provide the speedup function of SRAM rows ally. The system is able to speed up the ULV core instantaneously and execute more applications with the ULV-Turbo cache. In our system-wide evaluation based on a real attitude and heading reference system workload on an asymmetric wearable system, the ULV-Turbo cache reduces the energy consumption of the entire system by approximately 36%.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2016.2642170