A COTS-Based Novel 3-D DRAM Memory Cube Architecture for Space Applications

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 9; pp. 2055 - 2068
• Main Authors: Agnesina, Anthony, Yamaguchi, James, Krutzik, Christian, Carson, John, Yang-Scharlotta, Jean, Lim, Sung Kyu
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Aerospace electronics; Application specific integrated circuits; Bandwidth; Circuit design; Control systems design; Controllers; Cubes; Dynamic random access memory; dynamic random-access memory (DRAM); Emulators; Fault tolerance; Integrated circuits; Memory devices; memory management; radiation effects; Radiation hardening; Random access memory; Space applications; Space missions; Testing; three-dimensional integrated circuit (3-D IC); Through-silicon vias
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2020.3002211

The first mainstream products in three-dimensional integrated circuit (3-D IC) design are memory devices where multiple memory tiers are horizontally integrated to offer manifold improvements when compared with their 2-D counterparts. Unfortunately, none of these existing 3-D memory cubes are ready for harsh space environments. This article introduces a new memory cube architecture for space, based on the vertical integration of multiple commercial-off-the-shelf, 3-D stacked, dynamic random-access memory (DRAM) memory devices with a custom radiation-hardened-by-design controller. Our solution offers high memory capacity, increased bandwidth, fault tolerance, and improved size-weight-and-power characteristics needed for space missions. Validation and functional evaluation of the application-specific integrated circuit (ASIC) controller will be conducted prior to tape-out on a custom FPGA-based emulator platform integrating the 3-D stack. The selected test methodology ensures high-quality register transfer level (RTL) as well as allows to subject the cube structure to radiation testing. The proposed design concept allows for flexibility in the choice of the DRAM die in the case of technology road-map changes or unsatisfactory radiation results.