Effective Radii of On-Chip Decoupling Capacitors Under Noise Constraint
As the clock frequency of a chip increases, the on-chip decoupling capacitor must be placed closer to the load to be effective. A method of efficiently defining the location of capacitor placement to meet specified noise limits is presented. Based on a single RL line model for the power distribution...
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Published in | IEEE transactions on very large scale integration (VLSI) systems Vol. 24; no. 12; pp. 3415 - 3423 |
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Main Authors | , , , , |
Format | Journal Article |
Language | English |
Published |
New York
IEEE
01.12.2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | As the clock frequency of a chip increases, the on-chip decoupling capacitor must be placed closer to the load to be effective. A method of efficiently defining the location of capacitor placement to meet specified noise limits is presented. Based on a single RL line model for the power distribution system, charging radius of the decoupling capacitor is calculated under the constraint of the target noise but not the constraint of being fully charged. Under the constraints of the length of the charging path and the target noise, discharging radius of the decoupling capacitor is figured out. The conversion coefficient that converts the radii of a decoupling capacitor in a single RL line model into the equivalent one in a meshed model is presented based on the expression that can exactly compute the impedance between any two points on an infinite meshed network. In this paper, it is shown that the conversion coefficient is a constant when the radius of the decoupling capacitor is taken as the per unit length of the meshed model. |
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ISSN: | 1063-8210 1557-9999 |
DOI: | 10.1109/TVLSI.2016.2559585 |