A Novel Time-Shared and LUT-Less Pipelined Architecture for LMS Adaptive Filter

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 1; pp. 188 - 197
• Main Authors: Sarma, Ranendra Kumar, Khan, Mohd. Tasleem, Shaik, Rafi Ahamed, Hazarika, Jinti
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive filter (ADF); Adaptive filters; Adders; Architecture; Complexity theory; Critical path; Critical path method; Delays; finite impulse response (FIR); Finite impulse response filters; least mean square (LMS); Lookup tables; Pipelines; Power consumption; Table lookup
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2019.2935399

This article presents a novel time-shared and lookup table (LUT)-less pipelined architecture for a least-mean-square (LMS) adaptive filter (ADF). The proposed approach first employs a time-shared architecture for the pipelined LMS ADF to compute each filter partial product and coefficient increment term using a single multiplier. Critical path analysis of this architecture is carried out to determine the pipeline requirements. Next, a novel LUT-less multiplier is suggested by exploiting the symmetries between the odd-multiples. Due to the symmetries between the odd-multiples, offset terms are added using an adder tree. For higher wordlength coefficients, only a few adders are required to generate the odd-multiples, and only one offset adder tree is required. Finally, a novel super-latch is developed to pipeline the LUT-less multiplier with adaptation delays of the pipelined LMS ADF. From the implementation results, it is found that the proposed design for the 32nd-order filter occupies 60.32% less area, consumes 61.93% less power, and utilizes 58.83% less sliced LUTs and 63.28% fewer flip-flops over the best existing design.