Configurable Folded IIR Filter Design

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 62; no. 12; pp. 1144 - 1148
• Main Authors: Basiri M, Mohamed Asan, Mahammad Sk, Noor
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2015; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Clocks; Delays; FIR filter; Hardware design languages; IIR filter; IIR filters; Multiply-accumulate circuit; Pipelines; Finite impulse response (FIR) filter; multiply–accumulate circuit (MAC); infinite-impulse response (IIR) filter
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2015.2468917

This brief proposes an efficient very-large-scale integration architecture for folded configurable infinite-impulse response (IIR) filter design, which is used in modern real-time digital signal processing applications such as loudspeaker equalization. The proposed configurable sixth-order IIR filter is designed with three cascaded second-order IIR filters, and the same is used to perform one sixth-order or three second-order or one fourth-order and one second-order IIR filter operations in parallel, where floating-point multiply-accumulate circuit (MAC) is used to design each second-order IIR filter. The proposed sixth-order IIR filter achieves a 58.4% reduction in energy per operation compared with conventional MAC-based architecture using 45-nm technology.