A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm

A 6-bit full-binary compact and low-power current-steering digital-to-analog converter (DAC) designed for 60-GHz Wireless Personal Area Network applications is presented. The closely located circuit components based on the stacked unit cell minimize the parasitic capacitance and enhance the high-fre...

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Published inIEEE transactions on very large scale integration (VLSI) systems Vol. 24; no. 2; pp. 794 - 798
Main Authors Kim, Si-Nai, Kim, Mee-Ran, Sung, Ba-Ro-Saim, Kang, Hyun-Wook, Cho, Min-Hyung, Ryu, Seung-Tak
Format Journal Article
LanguageEnglish
Published New York IEEE 01.02.2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
CMOS integrated circuits
Current measurement
Current steering
digital-to-analog converter (DAC)
full binary
Linearity
Power demand
Resistance
Switches
Very large scale integration
wideband dynamic linearity
Current steering
full binary
digital-to-analog converter (DAC)
wideband dynamic linearity
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Summary:A 6-bit full-binary compact and low-power current-steering digital-to-analog converter (DAC) designed for 60-GHz Wireless Personal Area Network applications is presented. The closely located circuit components based on the stacked unit cell minimize the parasitic capacitance and enhance the high-frequency dynamic linearity. The proposed binary structure realizes a compact DAC by eliminating the need for additional circuits, such as thermometer decoders, and thus reduces power consumption. A prototype 6-bit 3.1-GS/s full-binary DAC was fabricated in a 90-nm CMOS process. The DAC exhibits a spurious-free dynamic range of >37.2 dB up to 3.1 GS/s over the Nyquist input. The chip consumes 17.7 mW of power and occupies 0.038 mm 2 of core size.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2015.2412657