A 58.9-dB ACR, 85.5-dB SBA, 5-26-MHz Configurable-Bandwidth, Charge-Domain Filter in 65-nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 48; no. 11; pp. 2827 - 2838
• Main Authors: Huang, Ming-Feng, Kuo, Ming-Ching, Yang, Tzu-Yi, Huang, Xuan-Lun
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2013; Institute of Electrical and Electronics Engineers
• Subjects: Adjacent-channel rejection (ACR); analog baseband; Applied sciences; Bandwidth; Calibration; charge-domain filter; Circuit properties; Clocks; Delays; Design. Technologies. Operation analysis. Testing; discrete-time filter; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Equalizers; Exact sciences and technology; Finite impulse response filters; finite-impulse response (FIR); Frequency filters; Gain; infinite-impulse response (IIR); Integrated circuits; reconfigurable filter; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; software-defined radio; stop-band attenuation (SBA); Infinite impulse response filter; infinite-impulse response (IIR); analog baseband; Feedback regulation; Clock; Adjacent-channel rejection (ACR); Implementation; Feedback; Complementary MOS technology; stop-band attenuation (SBA); reconfigurable filter; discrete-time filter; Delay time; Reconfigurable architectures; Multistage circuit; Pulse width; Multistage method; Discrete time systems; Base band; Discrete time filter; Calibration; Pulse modulation; finite-impulse response (FIR); Sampling rate; Insertion loss; charge-domain filter; Finite impulse response filter; software-defined radio; Gain; Continuous phase modulation
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2013.2280157

A configurable-bandwidth charge-domain filter (CDF) with bandwidth calibration and clock-pulse modulation (CPM) is proposed. The bandwidth calibration scheme controls the insertion loss at a pre-specified frequency by modulating the feedback gain and delay; this helps the CDF to suppress the sinc distortion and thus achieve near-ideal brick-wall filtering. For multi-frequency compensation, a multi-stage CDF architecture is utilized to organize the feedback delay. Together with non-decimation filtering, the noise folding effect as well as the chip area can be reduced. On the other hand, to provide a stable gain under variable channel bandwidth, a CPM scheme is proposed; it adjusts the clock period with a fixed pulse width by zero-insertion. Implemented in a 65-nm CMOS technology, the proposed CDF achieves 58.9-dB adjacent-channel rejection (ACR), 85.5-dB stop-band attenuation (SBA), 41-dB conversion gain, and 19.5-MHz channel bandwidth at 320-MS/s input-sampling rate. Furthermore, for input-sampling rates range from 300 to 480 MS/s, the channel bandwidth can be configured from 5 to 26 MHz. At 1.2-V supply, the chip consumes 8.4-mW power and occupies 0.52-mm 2 area.