Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 27; no. 8; pp. 1828 - 1839
• Main Authors: Ko, Junyoung, Yang, Younghwi, Kim, Jisu, Lee, Cheonan, Min, Young-Sun, Chun, Jinyoung, Kim, Moo-Sung, Jung, Seong-Ook
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Capacitance; Circuits; Computer simulation; Couplings; Electrical resistance measurement; Flash memory (computers); Incremental step pulse program (ISPP) method; nand flash; Programming; Random access memory; Resistance; Threshold voltage; under-driving scheme; WL driving scheme; word-line (WL) driving method
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2019.2912081

Research on a word-line (WL) driving scheme is essential because the effect of WL parasitic resistance and capacitance ( RC ) is more severe for high-capacity NAND flash memories. The WL under-driving scheme (WLUDS) mitigates the effect of parasitic RC by reducing the coupling capacitance between WLs. However, WLUDS increases the cell threshold voltage (<inline-formula> <tex-math notation="LaTeX">V_{\mathrm {th}} </tex-math></inline-formula>) distribution because of parasitic RC variation, which causes an overshoot of the programming voltage (<inline-formula> <tex-math notation="LaTeX">V_{\mathrm {PGM}} </tex-math></inline-formula>). In this study, we propose the variation-tolerant WL under-driving scheme (VTWLUDS) to reduce the effect of parasitic RC variation and <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {PGM}} </tex-math></inline-formula> overshoot through the use of a three-phase <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {PGM}} </tex-math></inline-formula> control. We also introduce the fast-verify WL driving scheme (FVWLDS) to reduce the effect of parasitic RC variation in the verify operation. We verified VTWLUDS and FVWLDS by performing an HSPICE simulation with Samsung's transistor model for a NAND peripheral circuit. The simulation results showed that VTWLUDS achieved a sufficient <inline-formula> <tex-math notation="LaTeX">V_{\mathrm {th}} </tex-math></inline-formula> shift during the programming operation regardless of the WL parasitic RC variation. By using VTWLUDS and FVWLDS, we achieved 1304 <inline-formula> <tex-math notation="LaTeX">\mu \text{s} </tex-math></inline-formula> of total programming time (<inline-formula> <tex-math notation="LaTeX">T_{\mathrm {PROG}} </tex-math></inline-formula>) for a 512-Gb planar-type NAND flash memory.