FPGA-Based Optimized Design of Montgomery Modular Multiplier

This brief introduces FPGA-based optimized implementation of Montgomery Modular Multiplier (MMM) architecture. The novel architecture of the proposed design enhanced the maximum frequency of the design and also the occupied area on the targeted FPGA. A Xilinx Virtex-6 FPGA implementation of the prop...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. II, Express briefs Vol. 68; no. 6; pp. 2137 - 2141
Main Authors Abd-Elkader, Ahmed A. H., Rashdan, Mostafa, Hasaneen, El-Sayed A. M., Hamed, Hesham F. A.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.06.2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
area
Computer architecture
Cryptography
Curves
Design optimization
ECC
Elliptic curve cryptography
Field programmable gate arrays
FPGA
Hardware
Internet of Things
Lightweight
Logic gates
MMM
Modular design
Multiplexing
Optimization
Registers
System on chip
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Summary:This brief introduces FPGA-based optimized implementation of Montgomery Modular Multiplier (MMM) architecture. The novel architecture of the proposed design enhanced the maximum frequency of the design and also the occupied area on the targeted FPGA. A Xilinx Virtex-6 FPGA implementation of the proposed architecture comparing with other related designs revealed that, our design occupies the smallest area, and the efficiency is enhanced in the range between 1.2 to 11.7 times the efficiency of other relevant designs. The proposed design is implemented as a modular multiplier for lightweight elliptic curve cryptography (ECC) over general GF(p). The proposed architecture is targeted the hardware implementation of lightweight cryptographic modules used on the System on Chip (SoC) and Internet of Things (IoT) devices.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2020.3040665