Reusing Trace Buffers as Victim Caches

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 26; no. 9; pp. 1699 - 1712
• Main Authors: Jindal, Neetu, Panda, Preeti Ranjan, Sarangi, Smruti R.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Buffer storage; Computer bugs; Debugging; Design for debug (DFD); Hardware; Instruction sets; Microprocessors; Observability (systems); Pipelines; postsilicon validation; Proposals; System on chip; victim cache; Visibility
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2018.2827928

With the increasing complexity of modern systems-on-chip, the possibility of functional errors escaping design verification is growing. Postsilicon validation targets the discovery of these errors in early hardware prototypes. Due to limited visibility and observability, dedicated design-for-debug (DFD) hardware, such as trace buffers, is inserted to aid postsilicon validation. In spite of its benefit, such hardware incurs area overheads that impose size limitations. However, the effective overhead could be reduced if the area dedicated to DFD could be reused in-field. In this paper, we present a novel method for reusing an existing trace buffer as a victim cache of a processor to enhance the performance. The trace buffer storage space is reused for the victim cache with a small additional controller logic. Simultaneous multithreading allows further fine-grained control of the victim cache, which can be shared between the threads based on the requirements of the applications. We also propose and evaluate different approaches to partition the victim cache between threads. Experimental results on several benchmark applications and trace buffer configurations show that the proposed approach can enhance the average performance by up to 8.3% with a minimal area overhead.