Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 28; no. 12; pp. 2658 - 2671
• Main Authors: Wu, Yi-Da, Yang, Kexin, Hsu, Shu-Han, Milor, Linda
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerated test; Accelerated tests; design of experiments; Dielectric breakdown; digital circuit; Digital electronics; Electric breakdown; Errors; Estimation; Fast Fourier transformations; Feature extraction; Forecasting; Fourier transforms; gate-oxide breakdown; Integrated circuit modeling; Integrated circuit reliability; Life estimation; Lifetime; lifetime simulator; Logic circuits; Logic gates; microprocessor; middle-of-line (MOL) time-dependent breakdown; Parameter estimation; Parameter identification; Process parameters; reliability; Time dependence; time-dependent dielectric breakdown (TDDB); wearout; Weibull distribution
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2020.3017950

A framework is presented to identify an optimal accelerated test region and accelerated test conditions for the accelerated test of logic circuits for time-dependent dielectric breakdown (TDDB). Both gate-oxide breakdown and middle-of-line (MOL) TDDB are investigated. Separate test regions are identified for each wearout mechanism. Two digital circuits, an 8-bit fast Fourier transform (FFT) circuit and a Leon3 microprocessor are used to demonstrate the capability of the framework. The lifetimes of standard cells are combined to compute the circuit lifetime, by combining the Weibull distributions that characterize the lifetime distribution of each of the standard cells. The errors in estimating wearout parameters consist of two parts: the error in estimating the wearout parameters at accelerated test conditions and the forecasting accuracy at use conditions. By estimating the errors in wearout parameters at accelerated test conditions, the optimal accelerated test region is found by determining the test conditions producing a minimal error. Test conditions are selected by minimizing the error at use conditions. Given a forecasting error target, the required sample size at each test condition is found. This work also considers the impact of variation in circuit size, type, and process parameters on the selection of optimal test conditions.