A 0.33-1 GHz Open-Loop Duty Cycle Corrector With Digital Falling Edge Modulator

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 65; no. 12; pp. 1949 - 1953
• Main Authors: Kang, Kyung-Tae, Kim, Sang-Yun, Kim, Sung Jin, Lee, Dongsoo, Yoo, Sang-Sun, Lee, Kang-Yoon
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Clocks; CMOS; Cycle ratio; Delays; Falling; falling edge modulator; Finite element analysis; Hardware reviews; Image edge detection; Interpolation; Logic gates; Modulation; Open-loop duty cycle corrector; phase interpolator; Power consumption; Signal integrity; Vibration
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2018.2811412

This brief presents an open-loop duty cycle corrector (DCC) with digital falling edge modulator. The proposed DCC consists of a loop delay chain for edge alignment and a falling edge modulator to enhance the phase interpolating limit. These features improved the duty offset correction range at high frequency besides low frequency with fast lock time and without degrading the signal integrity of the junction of a phase interpolator. The proposed DCC was fabricated in a TSMC 55-nm CMOS technology with 1-V supply voltage and the area occupied 0.0186 mm 2 . The measured results show that the duty cycle error of the output clock was adjusted to less than 2% when the duty cycle ratio of the input clock was changed from 80% to 20% at 1 GHz, and the lock cycle consumed only five cycles. At 1 GHz, the power consumption was 2.09 mW and the peak-to-peak jitter was measured at 12.53 ps.