Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 26; no. 11; pp. 2572 - 2576
• Main Authors: Mrazek, Vojtech, Vasicek, Zdenek, Sekanina, Lukas, Jiang, Honglan, Han, Jie
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adders; Approximate computing; Approximate computing circuits and systems; Approximation; Circuit design; circuit synthesis; Circuits; Computers; computers and information processing; Construction methods; Delays; Design methodology; Errors; Libraries; Multipliers; Power consumption; Very large scale integration
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2018.2856362

Approximate computing exploits the fact that many applications are inherently error resilient. In order to reduce power consumption, approximate circuits such as multipliers have been employed in these applications. However, most current approximate multipliers are based on <inline-formula> <tex-math notation="LaTeX">ad~hoc </tex-math></inline-formula> circuit structures and, for automated circuit approximation methods, large efficient designs are difficult to find due to the increased search space. Moreover, existing design methods do not typically provide sufficient formal guarantees in terms of error if large approximate multipliers are constructed. To address these challenges, this brief introduces a general and efficient method for constructing large high-quality approximate multipliers with respect to the objectives formulated in terms of the power-delay product and a provable error bound. This is demonstrated by means of a comparative evaluation of approximate 16-bit multipliers constructed by the proposed method and other methods in the literature.