A DNN-Based Low Power ECG Co-Processor Architecture to Classify Cardiac Arrhythmia for Wearable Devices

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 69; no. 4; pp. 2281 - 2285
• Main Authors: Janveja, Meenali, Parmar, Rushik, Tantuway, Mayank, Trivedi, Gaurav
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Arrhythmia; Artificial neural networks; ASIC; Biomedical monitoring; Cardiac arrhythmia; Classification; Classifiers; Design optimization; DNN; ECG; Electrocardiography; Feature extraction; Hardware; low power; Microprocessors; Neurons; Power demand; Power management; Wearable computers; Wearable technology
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2022.3146036

In this brief, a Deep Neural Network (DNN) based cardiac arrhythmia (CA) classifier is proposed, which can classify ECG beats into normal and different types of arrhythmia beats. An optimized fixed length beat is extracted from a time domain ECG signal and is fed as an input to the proposed classifier. This fixed sized input beat obviates the need to extract handcrafted ECG features and aids in the optimization of our proposed design. The classifier presented in this brief exhibits better or comparable classification accuracy than the previously reported methods, which utilize complex algorithms for CA classification employing patient-independent(subject-oriented) approaches. Moreover, the proposed CA classifier consumes <inline-formula> <tex-math notation="LaTeX">8.75~\mu W </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">12kHz </tex-math></inline-formula>, when implemented using <inline-formula> <tex-math notation="LaTeX">180nm </tex-math></inline-formula> Bulk CMOS technology. The low power realization of the proposed design as compared to well-known state-of-the-art methods makes it suitable for wearable healthcare device applications.