Design and Analysis of Self-Tanked Stepwise Charging Circuit for Four-Phase Adiabatic Logic

Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often a point of diffic...

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Bibliographic Details
Published inJournal of low power electronics and applications Vol. 14; no. 3; p. 34
Main Authors Morell, William, Choi, Jin-Woo
Format Journal Article
LanguageEnglish
Published Basel MDPI AG 01.09.2024
Subjects
Adiabatic flow
adiabatic logic
Best practice
Capacitors
Charging
Circuits
Clock drivers
Clocks
Clocks & watches
CMOS
Complementary metal oxide semiconductors
Design standards
Driver circuits
Embedded systems
Energy conservation
Energy consumption
Energy efficiency
FinFET
Logic
Power consumption
Power supply
stepwise charging
tank capacitor
Transistors
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Summary:Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often a point of difficulty in the design process. A novel, stepwise charging driver circuit for four-phase adiabatic logic is proposed and validated through a simulation study. The proposed circuit consists of two identical driver circuits each driving two opposite adiabatic logic phases. Its performance relative to ideal step-charging and a standard CMOS across mismatched phase loads is analyzed, and new best practices are established. It is compared to a reference circuit consisting of one driver circuit for each phase along with a paired on-chip tank capacitor. The proposed driver uses opposite logic phases to act as the tank capacitor for each other in a “self-tanked” fashion. Each circuit was simulated in 15 nm FinFET across a variety of frequencies for an arbitrary logic operation. Both circuits showed comparable power consumption at all frequencies tested, yet the proposed driver uses fewer transistors and control signals and eliminates the explicit tank capacitors entirely, vastly reducing circuit area, complexity, and development time.
ISSN:2079-9268
2079-9268
DOI:10.3390/jlpea14030034